ARCHITECTURE REGISTER / revision 2149.3
More work inside the thermal envelope.
Spiking processing architectures for system designers. Select a core family, inspect its dispatch fabric and compare the declared active workload before opening a licence review.
Browse horizontally to read all architecture and thermal columns.
| Architecture | Mean model power / W | Heat allocation / year |
|---|---|---|
| S8 / 8 cores / 1 GHz | 18.0 | 0.0062415 MW·day/year |
| Comparator / same load | 28.0 | 0.0097090 MW·day/year |
Event fabric, explicit interfaces
A bounded event queue feeds independent core pairs. Accumulators merge partial results at a declared barrier; a stalled output holds its queue instead of duplicating a dispatch. The logical drawing records connectivity, not transistor placement. Integrators provide their own memory timing, cooling and driver validation.
Release 2149.3
This revision separates idle power from activity-dependent power and publishes the comparator parameters with every calculation. Download the complete parameter record.